In the field of semiconductor memory devices (referred to as “memories” hereinafter), such as dynamic random access memories (DRAMs), demands for increased storage capacity are growing. For large-scale memories (memories having a large capacity), it is desirable to have a redundancy function to replace a defective cell which has occurred in a memory cell array with a redundancy cell to implement manufacturing yield improvement. An address corresponding to the defective cell is programmed into a redundancy fuse, which is blown by laser light irradiation. The address, which is programmed into the fuse, is read at the start time of memory chip operation, and is stored into a fuse latch. The address stored in the fuse latch is compared with a memory-cell access address input from an external source. If the two addresses match, the redundancy cell instead of the defective cell is accessed, whereby compensation for the defective cell is performed.
Ordinarily, if a defective cell exists, substitution of redundancy cells is performed in units on the basis of either one row or one column in a memory cell array of memory cells containing the defective cell. In the case of row-basis substitution, that is, in the case of row redundancy, a row address is programmed into fuses. In the case of column-basis substitution, that is, in the case of column redundancy, a column address is programmed into fuses.
Jpn. Pat. Appln. KOKAI Publication No. 11-86588 describes an algorithm to share fuses among redundancy elements to save the number of address fuses used to substitute redundancy elements for a defective element.
In addition, Jpn. Pat. Appln. KOKAI Publication No. 2000-207896 discloses a technique capable of repairing an error that occurs in burn-in testing of a semiconductor device packaged after laser repair in a wafer stage.
Further, U.S. Pat. No. 6,418,069 discloses a technique wherein a row line or column line containing a defective cell is replaced with one of redundant lines by programming. If an additional defective cell is detected after a predetermined number of redundant lines have been programmed, the programming of at least one of the redundant lines is canceled, and the redundant line is programmed for repairing another memory cell defect.